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DATA SHEET
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MOS INTEGRATED CIRCUIT
mPD78042F, 78043F, 78044F, 78045F
8-BIT SINGLE-CHIP MICROCOMPUTER
The mPD78042F, mPD78043F, mPD78044F, and mPD78045F are 8-bit single-chip microcomputers that incorporate many hardware peripherals such as an FIP(R) controller/driver, 8-bit resolution A/D converter, timer, serial interface, and interrupt controller. The one-time PROM and EPROM models that can operate in the same voltage range as that of masked ROM models, and various development tools are provided. The functions of these microcomputers are described in detail in the following User's Manual. Be sure to read this manual when you design a system using any of these microcomputers.
mPD78044F Sub-Series User's Manual : U10908E 78K/0 Series User's Manual, Instruction: IEU-1372
FEATURES
* High-capacity ROM and RAM
Item Product name Program memory (ROM) 16K bytes 24K bytes 32K bytes 40K bytes 1024 bytes Data memory Internal high-speed RAM 512 bytes Buffer RAM 64 bytes FIP display RAM 48 bytes
mPD78042F mPD78043F mPD78044F mPD78045F
* Wide range of instruction execution time - from
high-speed (0.4 ms) to ultra low-speed (122 ms)
* I/O ports: 68 * FIP controller/driver: total display outputs: 34
APPLICATIONS
* * * *
8-bit resolution A/D converter: 8 channels Serial interface: 2 channels Timer: 6 channels Power supply voltage: VDD = 2.7 to 5.5 V 5
CD players, cassete tape recorders, tuners, minicomponent stereos, VCRs, microwave ovens, ECRs, etc.
ORDERING INFORMATION
Part number Package 80-pin plastic QFP (14 20 mm) 80-pin plastic QFP (14 20 mm) 80-pin plastic QFP (14 20 mm) 80-pin plastic QFP (14 20 mm)
mPD78042FGF--3B9 mPD78043FGF--3B9 mPD78044FGF--3B9 mPD78045FGF--3B9
Remark indicates ROM code number.
The information in this document is subject to change without notice.
Document No. U10700EJ1V0DS00 (1st edition) Date Published July 1996 P Printed in Japan
The mark 5 shows major revised points.
(c)
1996 1990
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mPD78042F, 78043F, 78044F, 78045F
5
78K/0 SERIES PRODUCT DEVELOPMENT
The 78K/0 series products were developed as shown below. The sub-series names are indicated in frames.
For control 100-pin 100-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
Products under mass production Products under development 2 The Y Subseries is compatible with the I C bus.
PD78078 PD78070A PD78058F PD78054 PD78018F PD78014 PD780001 PD78002 PD78083
For FIP driving
PD78078Y PD78070AY PD78058FY PD78054Y PD78018FY PD78014Y PD78002Y
A timer added to the PD78054 and external interface functions enhanced. ROM-less product of the PD78078 Counter-measure against EMI noise added to the PD78054 An UART and D/A converter added to the PD78014 and I/O function enhanced. Low-voltage (1.8 V) versions of the PD78014. ROM and RAM variations enhanced. An A/D converter and 16-bit timer added to the PD78002. An A/D converter added to the PD78002 Basic subseries for control These products include an UART and can operate at a low voltage (1.8 V). The I/O and FIP C/D of the PD78044F enhanced. Total indication output pins: 53 A 6-bit U/D counter added to the PD78024. Total indication output pins: 34 Basic subseries for FIP driving. Total indication output pins: 26
78K/0 series
100-pin 80-pin 64-pin
PD780208 PD78044F PD78024
For LCD driving
100-pin 100-pin 100-pin
PD780308 PD78064B PD78064
PD780308Y PD78064Y
SIO of the PD78064 enhanced and ROM/RAM expanded. Counter-measure against EMI noise added to the PD78064. Basic subseries for LCD driving. These products include an UART.
Compatible with IEBusTM 80-pin
PD78098
For LV
An IEBus controller added to the PD78054.
100-pin
PD78P0914
PWM output, LV digital code decoder, built-in Hsync counter.
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mPD78042F, 78043F, 78044F, 78045F
The table below shows the main differences between subseries.
Function Subseries name For control ROM capacity 32K-60K - 48K-60K 16K-60K 8K-60K 8K-32K 8K 8K-16K 8K-16K 32K-60K 16K-40K 24K-32K 48K-60K 32K 16K-32K 32K-60K 2ch 1ch 1ch 1ch 8ch 2ch 3ch (UART : 1ch) 69 pins 2.7 V 2ch 1ch 1ch 1ch 8ch - 3ch (UART : 1ch) 2ch (UART : 1ch) 2ch 1ch - - 1ch - 1ch 1ch - 8ch 8ch - 1ch (UART : 1ch) 2ch 1ch 39 pins 53 pins 33 pins 74 pins 68 pins 54 pins 57 pins 1.8 V 2.0 V - 1.8 V 2.7 V - - - 2ch 53 pins 2ch Timer 8-bit 16-bit Watch WDT 4ch 1ch 1ch 1ch 8-bit A/D 8ch 8-bit D/A 2ch Serial interface 3ch (UART : 1ch) VDD Min. External value expansion 1.8 V 2.7 V
I/O 88 pins 61 pins 69 pins
mPD78078 mPD78070A mPD78058F mPD78054 mPD78018F mPD78014 mPD780001 mPD78002 mPD78083
5
2.0 V 1.8 V 2.7 V -
For FIP driving
mPD780208 mPD78044F mPD78024
For LCD driving
mPD780308 mPD78064B mPD78064
5
Compatible with IEBus For LV
mPD78098
mPD78P0914
32K
6ch
-
-
1ch
8ch
-
2ch
54 pins
4.5 V
5
3
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mPD78042F, 78043F, 78044F, 78045F
FUNCTIONAL OUTLINE
Product name Item Internal memory ROM Internal high-speed RAM Buffer RAM FIP display RAM General registers Instruction cycle
mPD78042F
16K bytes 512 bytes 64 bytes 48 bytes
mPD78043F
24K bytes
mPD78044F
32K bytes 1024 bytes
mPD78045F
40K bytes
8 bits 32 registers (8 bits 8 registers 4 banks) Variable instruction execution time
For main system clock For subsystem clock
0.4 ms/0.8 ms/1.6 ms/3.2 ms/6.4 ms (at 5.0 MHz) 122 ms (at 32.768 kHz) * Multiplication/division (8 bits 8 bits, 16 bits / 8 bits) * Bit (set, reset, test, Boolean algebra)
Instruction set
I/O ports (including those multiplexed with FIP pins)
Total * CMOS input * CMOS I/O * N-ch open-drain * P-ch open-drain I/O * P-ch open-drain output
: 68 lines : 2 lines
: 27 lines : 5 lines
: 16 lines : 18 lines
FIP controller/driver
Total * Segments * Digits
: 34 lines : 9 to 24 lines : 2 to 16 lines
A/D converter
* 8-bit resolution 8 channels * Power supply voltage: AVDD = 4.0 to 5.5 V
5
Serial interface
* 3-wire serial I/O/SBI/2-wire serial I/O selectable modes: 1 channel * 3-wire serial I/O mode (with automatic transmission/ reception function of up to 64 bytes) : 1 channel : 1 channel : 2 channels : 1 channel : 1 channel : 1 channel
Timer
* 16-bit timer/event counter * 8-bit timer/event counter * Watch timer * Watchdog timer * 6 bit up/down counter
Timer output Clock output
3 lines (one for 14-bit PWM output) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz (Main system clock: at 5.0 MHz) 32.768 kHz (Subsystem clock: at 32.768 kHz)
Buzzer output Vectored interrupt Maskable interrupt Non-maskable interrupt Software interrupt Text input
1.2 kHz, 2.4 kHz, 4.9 kHz (Main system clock: at 5.0 MHz) Internal 10 lines, external 4 lines Internal 1 line 1 line Internal 1 line VDD = 2.7 to 5.5 V 80-pin plastic QFP (14 20 mm)
5
Power supply voltage Package
4
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mPD78042F, 78043F, 78044F, 78045F
CONTENTS
1. 2. 3.
PIN CONFIGURATION (TOP VIEW) ........................................................................................ BLOCK DIAGRAM ..................................................................................................................... PINS FUNCTIONS .....................................................................................................................
3.1 3.2 3.3 PORT PINS ...................................................................................................................................... PINS OTHER THAN PORT PINS ................................................................................................... PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS ........................................................
6 8 9
9 11 13
4. 5.
MEMORY SPACE ...................................................................................................................... PERIPHERAL HARDWARE FUNCTIONS ...............................................................................
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 PORTS ............................................................................................................................................. CLOCK GENERATOR CIRCUIT .................................................................................................... TIMER/EVENT COUNTER .............................................................................................................. CLOCK OUTPUT CONTROL CIRCUIT ......................................................................................... BUZZER OUTPUT CONTROL CIRCUIT ....................................................................................... A/D CONVERTER ........................................................................................................................... SERIAL INTERFACE ...................................................................................................................... FIP CONTROLLER/DRIVER ..........................................................................................................
16 17
17 18 18 21 21 22 22 24
6.
INTERRUPT FUNCTION AND TEST FUNCTION ....................................................................
6.1 6.2 INTERRUPT FUNCTION................................................................................................................. TEST FUNCTION ............................................................................................................................
26
26 29
7. 8. 9.
STANDBY FUNCTION ............................................................................................................... RESET FUNCTION .................................................................................................................... INSTRUCTION SET ...................................................................................................................
30 30 31 34 58 63 64 65 67
5 5 5
10. ELECTRICAL SPECIFICATIONS ............................................................................................. 11. CHARACTERISTIC CURVE (REFERENCE VALUE) .............................................................. 12. PACKAGE DRAWING ............................................................................................................... 13. RECOMMENDED SOLDERING CONDITIONS ........................................................................ APPENDIX A DEVELOPMENT TOOLS ......................................................................................... APPENDIX B RELATED DOCUMENTS .........................................................................................
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mPD78042F, 78043F, 78044F, 78045F
1. PIN CONFIGURATION (TOP VIEW)
* 80-pin plastic QFP (14 20 mm)
mPD78042FGF--3B9, mPD78043FGF--3B9 mPD78044FGF--3B9, mPD78045FGF--3B9
P100/FIP10
P101/FIP11
P102/FIP12
P103/FIP13
P104/FIP14
P105/FIP15
P106/FIP16
P107/FIP17
P110/FIP18
P111/FIP19
P112/FIP20
P94/FIP6 P93/FIP5 P92/FIP4 P91/FIP3 P90/FIP2 P81/FIP1 P80/FIP0 VDD P27/SCK0 P26/SO0/SB1 P25/SI0/SB0 P24/BUSY P23/STB P22/SCK1 P21/SO1 P20/SI1 RESET P74 P73 AVSS P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4
1 2 3 4 5 6 7 8 9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
P113/FIP21
P95/FIP7
P96/FIP8
P97/FIP9
VLOAD
P114/FIP22 P115/FIP23 P116/FIP24 P117/FIP25 P120/FIP26 P121/FIP27 P122/FIP28 P123/FIP29 P124/FIP30 P125/FIP31 P126/FIP32 P127/FIP33 VDD P70 P71 P72 IC P00/INTP0/TI0 P01/INTP1 P02/INTP2 P03/INTP3/CI0 P30/TO0 P31/TO1 P32/TO2
10 11 12 13 14 15 16 17 18 19 20 21 22 23
24 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
P04/XT1
P34/TI2
XT2
P36/BUZ
Cautions 1. Connect the IC (Internally Connected) pins directly to the VSS. 2. Connect the AVDD pin to the VDD pin. 3. Connect the AVSS pin to the VSS pin.
6
P35/PCL
P33/TI1
AVDD
AVREF
VSS
X1
X2
P37
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mPD78042F, 78043F, 78044F, 78045F
: Port 0 : Port 1 : Port 2 : Port 3 : Port 7 : Port 8 : Port 9 : Port 10 : Port 11 : Port 12 : Timer input : Timer output : Counter input : Serial bus : Serial input : Serial output SCK0, SCK1 : Serial clock PCL BUZ STB BUSY VLOAD X1, X2 XT1, XT2 RESET ANI0-ANI7 AVDD AVSS AVREF VDD VSS IC : Programmable clock : Buzzer clock : Strobe : Busy : Negative power supply : Crystal (main system clock) : Crystal (subsystem clock) : Reset : Analog input : Analog power supply : Analog ground : Analog reference voltage : Power supply : Ground : Internally connected
P00-P04 P10-P17 P20-P27 P30-P37 P70-P74 P80, P81 P90-P97 P100-P107 P110-P117 P120-P127 TI0-TI2 TO0-TO2 CI0 SB0, SB1 SI0, SI1 SO0, SO1
FIP0-FIP33 : Fluorescent indicator panel
INTP0-INTP3 : Interrupt from peripherals
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mPD78042F, 78043F, 78044F, 78045F
2. BLOCK DIAGRAM
TO0/P30 TI0/INTP0/P00 TO1/P31 TI1/P33 TO2/P32 TI2/P34
16-bit timer/ event counter
Port 0
P00 P01-P03 P04 P10-P17
8-bit timer/ event counter 1 8-bit timer/ event counter 2
Port 1
Port 2
P20-P27
Watchdog timer
Port 3
P30-P37
Watch timer 6-bit up/down counter 78K/0 CPU core ROM
Port 7
P70-P74
CI0/INTP3/P03 SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP0/TI0/P00INTP3/CI0/P03 BUZ/P36
Port 8
P80, P81
Serial interface 0
Port 9
P90-P97
Port 10 Serial interface 1
P100-P107
Port 11
P110-P117
Port 12 RAM FIP controller/driver Interrupt control
P120-P127
A/D converter
FIP0-FIP33 VLOAD
Buzzer output Clock output control
System control VDD VSS IC
PCL/P35
RESET X1 X2 XT1/P04 XT2
Remark The capacities of the internal ROM and RAM differ depending on the product.
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mPD78042F, 78043F, 78044F, 78045F
3. PINS FUNCTIONS
3.1 PORT PINS (1/2)
I/O Input I/O Port 0 5-bit I/O port Input only Can be specified for input or output in 1-bit units. When used as an input port pin, a built-in pull-up resistor can be used by software. Input I/O Port 1 8-bit I/O port Can be specified for input or output in 1-bit units. When used as an input port pin, a built-in pull-up resistor can be used by software.Note 2 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 I/O Port 3 8-bit I/O port Can be specified for input or output in 1-bit units. Can directly drive LEDs. When used as an input port pin, a built-in pull-up resistor can be used by software. A pull-down resistor can be connected in 1-bit units by the mask option. Input I/O Port 2 8-bit I/O port Can be specified for input or output in 1-bit units. When used as an input port pin, a built-in pull-up resistor can be used by software. Input SI1 SO1 SCK1 STB BUSY SI0/SB0 SO0/SB1 SCK0 TO0 TO1 TO2 TI1 TI2 PCL BUZ -- Input only Input Input Function On reset Input Input Shared by: INTP0/TI0 INTP1 INTP2 INTP3/CI0 XT1 ANI0-ANI7
Pin name P00 P01 P02 P03 P04Note 1 P10-P17
Notes 1. When the P04/XT1 pins is used as an input port pin, bit 6 (FRC) of the processor clock control register (PCC) must be set to 1. At this time, do not use the feedback resistor of the subsystem clock oscillator circuit. 2. When the P10/ANI0 through P17/ANI7 pins are used as the analog input lines of the A/D converter, be sure to place the port 1 in the input mode. In this case, the built-in pull-up resistors are automatically unused.
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mPD78042F, 78043F, 78044F, 78045F
3.1
PORT PINS (2/2)
I/O I/O Function Port 7 5-bit N-ch open-drain I/O port Can be specified for input or output in 1-bit units. Can directly drive LEDs. A pull-up resistor can be connected in 1-bit units by the mask option. On reset Input Shared by: --
Pin name P70-P74
P80, P81
Output
Port 8 2-bit P-ch open-drain high-voltage output port. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether VLOAD or VSS is connected can be specified in bit units).
Output
FIP0, FIP1
P90-P97
Output
Port 9 8-bit P-ch open-drain high-voltage output port. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether VLOAD or VSS is connected can be specified in 4-bit units).
Output
FIP2-FIP9
P100-P107
Output
Port 10 8-bit P-ch open-drain high-voltage output port. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether VLOAD or VSS is connected can be specified in 4-bit units). Port 11 8-bit P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit units. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether VLOAD or VSS is connected can be specified in 4-bit units). Port 12 8-bit P-ch open-drain high-voltage I/O port Can be specified for input or output in 1-bit units. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether VLOAD or VSS is connected can be specified in 4-bit units).
Output
FIP10-FIP17
P110-P117
I/O
Input
FIP18-FIP25
P120-P127
I/O
Input
FIP26-FIP33
10
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mPD78042F, 78043F, 78044F, 78045F
3.2
PINS OTHER THAN PORT PINS (1/2)
Pin name INTP0 INTP1 INTP2 INTP3 SI0 SI1 SO0 SO1 SB0 SB1 SCK0 SCK1 STB
I/O Input
Function Valid edge (rising, falling, or both rising and falling edges) can be specified. External interrupt input Falling edge-active external interrupt input
On reset Input
Shared by: P00/TI0 P01 P02
Input Input
P03/CI0 P25/SB0 P20
Input
Serial data input lines of serial interface
Output
Serial data output lines of serial interface
Input
P26/SB1 P21
I/O
Serial data I/O lines of serial interface
Input
P25/SI0 P26/SO0
I/O
Serial clock I/O lines of serial interface
Input
P27 P22
Output
Automatic transmission/reception strobe output line of serial interface Automatic transmission/reception busy input line of serial interface External count clock input to 16-bit timer (TM0) External count clock input to 8-bit timer (TM1) External count clock input to 8-bit timer (TM2)
Input
P23
BUSY TI0 TI1 TI2 TO0 TO1 TO2 CI0 PCL
Input Input
Input Input
P24 P00/INTP0 P33 P34
Output
16-bit timer output (multiplexed with 14-bit PWM output) 8-bit timer output
Input
P30 P31 P32
Input Output
Clock input to 6-bit up/down counter Clock output (for trimming main system clock and subsystem clock) Buzzer output High-voltage, high-current digit/segment output of FIP controller/driver
Input Input
P03/INTP3 P35
BUZ FIP0, FIP1 FIP2-FIP9 FIP10-FIP15
Output Output
Input Output
P36 P80, P81 P90-P97
Output
High-voltage, high-current digit/segment output of FIP controller/driver High-voltage segment output of FIP controller/driver
Output
P100-P105
FIP16, FIP17 FIP18-FIP25 FIP26-FIP33 VLOAD
Output
Output Input
P106, P107 P110-P117 P120-P127
--
Connects pull-down resistor to FIP controller/driver
--
--
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mPD78042F, 78043F, 78044F, 78045F
3.2
PINS OTHER THAN PORT PINS (2/2)
Pin name I/O Input Input -- -- Input Input -- Input -- -- -- -- Positive power supply Ground potential Internal connection. Connected directly to the VSS pin. Connect crystal for subsystem clock oscillation Function A/D converter analog input lines A/D converter reference voltage input line Analog power supply to A/D converter. Connected to the VDD pin. A/D converter ground line. Connected to the VSS pin. System reset input Connect crystal for main system clock oscillation On reset Input -- -- -- -- -- -- Input -- -- -- -- P04 -- -- -- -- Shared by: P10-P17 -- -- -- -- -- --
ANI0-ANI7 AVREF AVDD AVSS RESET X1 X2 XT1 XT2 VDD VSS IC
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mPD78042F, 78043F, 78044F, 78045F
3.3
PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS
Table 3-1 shows the I/O circuit type of each pin and the processing of unused pins. For the configuration of the I/O circuit of each type, refer to Fig. 3-1. Table 3-1
Pin name P00/INTP0/TI0 P01/INTP1 P02/INTP2 P03/INTP3/CI0 P04/XT1 P10/ANI0-P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P70-P74 P80/FIP0, P81/FIP1 P90/FIP2-P97/FIP9 P100/FIP10-P107/FIP17 P110/FIP18-P117/FIP25 P120/FIP26-P127/FIP33 RESET XT2 AVREF AVDD AVSS VLOAD IC Connected directly to VSS. 2 16 -- Input -- Open Connected to VSS. Connected to VDD. Connected to VSS. -- 15-C I/O Individually connected to VDD or VSS with a resistor. 13-B 14-A Output Open 5-C 8-B 5-C 16 11 8-A 5-A 8-A 5-A 8-A 10-A Input I/O Connected to VDD or VSS. Individually connected to VDD or VSS with a resistor. I/O Circuit type 2 8-A
I/O Circuit Type
I/O Recommended connections when unused Connected to VSS. Individually connected to VSS with a resistor.
Input I/O
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mPD78042F, 78043F, 78044F, 78045F
Fig. 3-1 Pin I/O Circuits (1/2)
Type 2
Type 8-A
Pull-up enable
VDD
P-ch VDD
IN
Data
P-ch IN/OUT
Schmitt trigger input with hysteresis characteristics
Output disable
N-ch
Type 5-A
Pull-up enable VDD
VDD
Type 8-B
VDD Pull-up enable VDD
P-ch
P-ch
Data
P-ch IN/OUT
Data
P-ch IN/OUT
Output disable
N-ch
Output disable
N-ch
(Mask option)
Input enable
Type 5-C
VDD Pull-up enable VDD Data P-ch IN/OUT Output disable Input enable
N-ch
Type 10-A
Pull-up enable VDD Data
VDD
P-ch
P-ch
P-ch IN/OUT
(Mask option)
Open-drain Output disable
N-ch
14
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mPD78042F, 78043F, 78044F, 78045F
Fig. 3-1 Pin I/O Circuits (2/2)
Type 11
Pull-up enable VDD Data P-ch
VDD P-ch
Type 15-C
VDD P-ch
VDD P-ch IN/OUT
Data
IN/OUT Output disable Comparator
+ -
N-ch
N-ch P-ch
(Mask option) VLOAD (Mask option)
N-ch VREF (Threshold voltage) Input enable
RD
N-ch
Type 13-B
VDD (Mask option) Data Output disable N-ch VDD
Type 16
Feedback cut-off
IN/OUT
P-ch
RD
P-ch
Input buffer with intermediate withstand voltage
XT1
XT2
Type 14-A
V DD P-ch Data N-ch
V DD P-ch OUT (Mask option) VLOAD (Mask option)
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mPD78042F, 78043F, 78044F, 78045F
4. MEMORY SPACE
Fig. 4-1 shows the memory map for mPD78042F, mPD78043F, mPD78044F, and mPD78045F. Fig. 4-1 Memory Map
FFFFH Special function register (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH General register 32 x 8 bits
Internal high-speed RAM Note nnnnH Inhibited Buffer RAM 64 x 8 bits 1000H 0FFFH CALLF entry area Inhibited FA80H FA7FH FA50H FA4FH FIP display RAM 48 x 8 bits Inhibited nnnnH + 1 nnnnH Program memory space 0000H Internal ROM Note Vector table area 0000H 0080H 007FH CALLT table area 0040H 003FH 0800H 07FFH Program area Program area
Data memory space
mmmmH mmmmH - 1 FB00H FAFFH
FAC0H FABFH
Note The internal ROM and internal high-speed RAM capacities vary depending on the product. (See the table below.)
Product name Last Address of Internal ROM nnnnH First address of internal high-speed RAM mmmmH FD00H
mPD78042F mPD78043F mPD78044F mPD78045F
3FFFH 5FFFH 7FFFH 9FFFH
FB00H
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mPD78042F, 78043F, 78044F, 78045F
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS I/O ports are classified into the following five types: * CMOS input (P00, P04) * CMOS input/output (P01 - P03, ports 1 - 3) * N-ch open-drain input/output (port 7) * P-ch open-drain output (ports 8 - 10) * P-ch open-drain input/output (ports 11 and 12) Total Table 5-1
Product Port 0 Pin P00, P04 P01-P03 Input-only port I/O port. Can be specified for input or output in 1-bit units. When used as input port, internal pull-up resistor can be connected through software. I/O port. Can be specified for input or output in 1-bit units. When used as input port, internal pull-up resistor can be connected through software. I/O port. Can be specified for input or output in 1-bit units. When used as input port, internal pull-up resistor can be connected through software. I/O port. Can be specified for input or output in 1-bit units. When used as input port, internal pull-up resistor can be connected through software. Pull-down resistor can be connected in 1-bit units by the mask option. Can directly drive LED. Port 7 P70-P74 N-ch open-drain I/O port. Can be specified for input or output in 1-bit units. Pull-up resistor can be connected in 1-bit units by the mask option. Can directly drive LED. Port 8 P80, P81 P-ch open-drain output port with high withstand voltage. Pull-down resistor can be connected in 2-bit units by the mask option (connection to VLOAD or VSS can be specified in 2-bit units). Can directly drive LED. P-ch open-drain output port with high withstand voltage. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LED. P-ch open-drain output port with high withstand voltage. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LED. P-ch open-drain I/O port with high withstand voltage. Can be specified for input or output in 1-bit units. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LED. P-ch open-drain I/O port with high withstand voltage. Can be specified for input or output in 1-bit units. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LED.
:2 : 27 :5 : 18 : 16 : 68 Port Function
Function
Port 1
P10-P17
Port 2
P20-P27
Port 3
P30-P37
Port 9
P90-P97
Port 10
P100-P107
Port 11
P110-P117
Port 12
P120-P127
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5.2
CLOCK GENERATOR CIRCUIT
The clock generator circuit has two kinds of generator circuits: the main system clock and subsystem clock. The instruction time can be changed. * 0.4 ms/0.8 ms/1.6 ms/3.2 ms/6.4 ms (with main system clock: 5.0 MHz) * 122 ms (with subsystem clock: 32.768 kHz) Fig. 5-1 Clock Generator Circuit Block Diagram
XT1/P04 XT2
Subsystem clock oscillator
fXT Clock output circuit
Selector
fX 16
Selector
fX 8
Noise eliminator
Watch timer
Prescaler X1 X2 Main system clock oscillator 1 Prescaler fX fX 2 STOP fX 22 fX 23 fX 24 fXT 2
Selector
2
Clock to hardware peripherals
Standby control circuit
CPU clock (f CPU)
To INTP0 sampling clock
5.3
TIMER/EVENT COUNTER
Six channels of timer/event counters are provided. * 16-bit timer/event counter : 1 channel * 8-bit timer/event counter : 2 channels * Watch timer * Watchdog timer * 6-bit up/down counter : 1 channel : 1 channel : 1 channel Timer/Event Counter Groups and Configurations
16-bit timer/ event counter Group Interval timer External event counter Timer output PWM output Function Pulse width measurement Square wave output Interrupt Request Test input 1 channel 1 channel 1 output 1 output 1 input 1 output 1 -- 8-bit timer/ event counter 2 channels 2 channels 2 outputs -- -- 2 outputs 2 -- 1 1 input Watch timer 1 channel -- -- -- -- -- 1 -- Watchdog timer 1 channel -- -- -- -- -- 1 -- 6-bit up/ down counter -- 1 channel -- -- -- --
Table 5-2
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Fig. 5-2 16-Bit Timer/Event Counter Block Diagram
Internal bus
16-bit compare register (CR00) PWM pulse output control circuit
INTTM0
Match fX
16-bit timer/event counter output control circuit
TO0/P30
fX/22 fX/23 TI0/P00/INTP0 Edge detector
Selector
fX/2
16-bit timer register (TM0) Selector INTP0
Clear
16-bit capture register (CR01)
Internal bus
Fig. 5-3
8-Bit Timer/Event Counter Block Diagram
Internal bus
INTTM1 8-bit compare register (CR10)
8-bit compare register (CR20)
Selector
Match Match
Output control circuit
TO2/P32
Selector
fX/2 -fX/210 fX/212 TI1/P33
INTTM2
Selector
8-bit timer register 1 (TM1) Clear
8-bit timer register 2 (TM2)
Selector
fX/2 -fX/210 fX/212 TI2/P34
Selector
Clear
Output control circuit Internal bus
TO1/P31
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Fig. 5-4 Watch Timer Block Diagram
Selector
fW
Selector
fX/28 fXT
Selector
5-bit counter
fW 214 INTWT
Prescaler
fW 24
fW 25
fW 26
fW 27
fW 28
fW 29
Selector
fW 213
INTTM3
Fig. 5-5
Watchdog Timer Block Diagram
Selector
fX 24 fX 23
fWDT
Prescaler fWDT 2 fWDT 22 fWDT 23 fWDT 24 fWDT 25 fWDT 26 fWDT 28
8-bit counter
Control circuit
Selector
INTWDT Maskable interrupt request RESET INTWDT Nonmaskable interrupt request
Fig. 5-6 6-Bit Up/Down Counter Block Diagram
Selector Clear CI0/P03/INTP3 Edge detector 6-bit up/down counter (UDC) Load Match Underflow 6-bit up/down counter compare register (UDCC)
INTP3/INTUD
Internal bus
Caution When using the 6-bit up/down counter, set the CI0/P03/INTP3 pin in the input mode (set bit 3 of port mode register 0 (PM03) to 1).
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5.4
CLOCK OUTPUT CONTROL CIRCUIT
Clocks of the following frequencies can be output to the clock: * 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz (with main system clock: 5.0 MHz) * 32.768 kHz (with subsystem clock: 32.768 kHz) Fig. 5-7 Clock Output Control Circuit Block Diagram
f X /2 3 f X /2 4
Selector
f X /2 f X /2 6 f X /2 f X /2 f XT
7 8
5
Sync circuit
Output control circuit
PCL/P35
5.5
BUZZER OUTPUT CONTROL CIRCUIT
Clocks of the following frequencies can be output to the buzzer: * 1.2 kHz/2.4 kHz/4.9 kHz (with main system clock: 5.0 MHz) Fig. 5-8 Buzzer Output Control Circuit Block Diagram
f X /2 11 f X /2 12
Selector
f X /2
10
Output control circuit
BUZ/P36
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5.6
A/D CONVERTER
An 8-bit resolution 8-channel A/D converter is provided. This A/D converter can be started in the following two modes: * Hardware start * Software start Fig. 5-9 A/D Converter Block Diagram
Series resistor string AVDD ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Successive approximation register (SAR) AVSS
Selector
AVREF Sample & hold circuit Voltage comparator
Tap selector
INTP3/P03
Falling edge detector
Control circuit
INTAD INTP3
A/D conversion result register (ADCR)
Internal bus
5.7
SERIAL INTERFACE
Two channels of clocked serial interfaces are provided. * Serial interface channel 0 * Serial interface channel 1 Table 5-3
Function 3-wire serial I/O mode SBI (serial bus interface) mode 2-wire serial I/O mode 3-wire serial I/O mode with automatic transmission/ reception function
Serial Interface Groups and Functions
Serial interface channel 0 Serial interface channel 1 * (MSB/LSB first selectable) -- -- -- * (MSB/LSB first selectable)
* (MSB/LSB first selectable) * (MSB first) * (MSB first)
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Fig. 5-10 Serial Interface Channel 0 Block Diagram
Internal bus
Selector
SI0/SB0/P25
Serial I/O shift register 0 (SIO0)
Output latch
SO0/SB1/P26
Selector
Bus release/ command/acknowledge detector Serial clock counter Interrupt request signal generator
Busy/acknowledge output circuit
INTCSI0
SCK0/P27
Serial clock control circuit
Selector
fX/22 -fX/29 TO2
Fig. 5-11
Serial Interface Channel 1 Block Diagram
Internal bus
Automatic data transmission/reception address pointer (ADTP)
Buffer RAM
Automatic data transmission/ reception interval specification register (ADTI)
SI1/P20 SO1/P21
Serial I/O shift register 1 (SIO1)
Match
5-bit counter STB/P23 Handshake control circuit Serial clock counter Interrupt request signal generator
BUSY/P24 SCK1/P22
INTCSI1
fX/22-fX/29 Serial clock control circuit
Selector
TO2
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5.8
FIP CONTROLLER/DRIVER
An FIP controller/driver having the following features is provided: (a) Automatic output of segment signals (DMA operation) and digit signals by automatically reading display data (b) Display mode registers (DSPM0 and DSPM1) that can control an FIP of 9 to 24 segments and 2 to 16 digits (c) Port pins not used for FIP display can be used as output port or I/O port pins. (d) Display mode register (DSPM1) can adjust luminance in eight steps. (e) Hardware suitable for key scan application using segment pins (f) High-voltage output buffer (FIP driver) that can directly drive an FIP (g) Display output pins can be connected to a pull-down resistor by the mask option. Fig. 5-12 Selecting Display Modes
Selecting number of digits
0 9 10 11 12 13
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Selecting number of segments
14 15 16 17 18 19 20 21 22 23 24
Caution If the total number of digits and segments exceeds 34, the specified number of digits takes precedence.
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Fig. 5-13 FIP Controller/Driver Block Diagram
Internal bus
Display data memory
Digit signal generator
Segment data latch
Port output latch
Buffer with high withstand voltage
FIP0/P80 FIP1/P81
FIP33/P127
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6. INTERRUPT FUNCTION AND TEST FUNCTION
6.1 INTERRUPT FUNCTION
The following three types of interrupt functions are available: * Non-maskable interrupt : 1 * Maskable interrupt * Software interrupt : 13 :1 Table 6-1 Interrupt Source List
Note 2
Note 1
Interrupt source Internal/ external Name INTWDT Trigger Watchdog timer overflow (with watchdog timer mode 1 selected) Watchdog timer overflow (with interval timer mode selected) Internal
Interrupt type
Default priority
Vector table address
Basic configuration type
Non-maskable
--
0004H
(A)
Maskable
0
INTWDT
(B)
1 2 3 4
INTP0 INTP1 INTP2 INTP3 INTUD
Pin input edge detection
External
0006H 0008H 000AH 000CH
(C) (D)
6-bit up/down counter match signal generation Internal End of serial interface channel 0 transfer End of serial interface channel 1 transfer Reference time interval signal from watch timer 16-bit timer/event counter match signal generation 8-bit timer/event counter 1 match signal generation 8-bit timer/event counter 2 match signal generation End of A/D converter conversion Key scan timing from FIP controller/driver Execution of BRK instruction -- 000EH 0010H 0012H
(B)
5 6 7
INTCSI0 INTCSI1 INTTM3
8
INTTM0
0014H
9
INTTM1
0016H
10
INTTM2
0018H
11 12 Software --
INTAD INTKS BRK
001AH 001CH 003EH (E)
Notes 1. Default priority is the priority order when several maskable interrupts are generated at the same time. 0 is the highest order and the 12 is the lowest order. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Fig. 6-1.
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Fig. 6-1 Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Interrupt request
Priority control circuit
Vector table address generator Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Interrupt request
IF
Priority control circuit
Vector table address generator Standby release signal
(C) External maskable interrupt (INTP0)
Internal bus
Sampling clock select register (SCS)
External interrupt mode register (INTM0)
MK
IE
PR
ISP
Interrupt request
Sampling clock
Edge detector
IF
Priority control circuit
Vector table address generator Standby release signal
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Fig. 6-1 Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupt (except INTP0)
Internal bus
External interrupt mode register (INTM0)
MK
IE
PR
ISP
Interrupt request
Edge detector
IF
Priority control circuit
Vector table address generator Standby release signal
(E) Software interrupt
Internal bus
Interrupt request
Priority control circuit
Vector table address generator
IF IE MK PR
: Interrupt request flag : Interrupt enable flag : Interrupt mask flag : Priority specification flag
ISP : In-service priority flag
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6.2
TEST FUNCTION
The following test function is available.
Test input source Name INTWT Trigger Overflow of watch timer
Internal/external
Internal
Fig. 6-2
Basic Configuration of Test Function
Internal bus
MK
Test input source (INTWT)
IF
Standby release signal
IF
: Test request flag
MK : Test mask flag
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7. STANDBY FUNCTION
The standby function is to reduce the current dissipation of the system and can be effected in the following two modes: * HALT mode : In this mode, the operating clock of the CPU is stopped. By using this mode in combination with the normal operation mode, the system can be operated intermittently, so that the average current dissipation can be reduced. * STOP mode : Oscillation of the main system clock is stopped. All the operations on the main system clock are stopped, and therefore, the current dissipation of the system can be minimized with only the subsystem clock oscillating. Fig. 7-1 Standby Function
Main system clock operation STOP instruction Interrupt request STOP mode (Oscillation of main system clock stopped)
CSS = 1 CSS = 0 HALT instruction
Subsystem clock operationNote HALT instruction
Interrupt request
Interrupt request HALT mode (Clock supply to CPU stopped. Oscillation continues) HALT modeNote (Clock supply to CPU stopped. Oscillation continues)
Note By stopping the main system clock, the current dissipation can be reduced. When the CPU operates on the subsystem clock, stop the main system clock by setting bit 7 (MCC) of the processor clock control register (PCC). The STOP instruction cannot be used. Caution When the main system clock is stopped and the subsystem clock is operating, to switch again from the subsystem clock to the main system clock, allow sufficient time for the oscillation to settle before switching, by coding the program accordingly.
8. RESET FUNCTION
The system can be reset in the following two modes: * External reset by RESET pin * Internal reset by watchdog timer that detects hang up
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9. INSTRUCTION SET
(1) 8-bit instruction MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second operand #byte First operand A ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP DBNZ MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV DBNZ INC DEC MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP A r
Note
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + byte] [HL + B] [HL + C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
$addr16
1
None
ROR ROL RORC ROLC
r
MOV
INC DEC
B, C sfr saddr
5
!addr16 PSW MOV
MOV MOV PUSH POP
[DE] [HL]
MOV MOV ROR4 ROL4
[HL + byte] [HL + B] [HL + C] X C
MOV
MULU DIVUW
Note Except for r = A
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(2) 16-bit instruction MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second operand #word First operand AX ADDW SUBW CMPW MOVW MOVW
Note
AX
rp
Note
sfrp
saddrp !addr16
SP
None
MOVW XCHW
MOVW
MOVW
MOVW
MOVW
rp
INCW DECW PUSH POP
sfrp saddrp !addr16 SP
MOVW MOVW
MOVW MOVW MOVW
MOVW
MOVW
Note Only when rp = BC, DE, HL
(3) Bit manipulation instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second operand A.bit First operand A.bit MOV1 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR SET1 CLR1 sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
sfr.bit
MOV1
SET1 CLR1
saddr.bit
MOV1
SET1 CLR1
PSW.bit
MOV1
SET1 CLR1
[HL].bit
MOV1
SET1 CLR1
CY
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
SET1 CLR1 NOT1
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(4) Call/Branch instruction CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second operand AX First operand Basic operation BR CALL BR CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ !addr16 !addr11 [addr5] $addr16
Compound operation
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
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5
10. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 C)
Parameter Power supply voltage Symbol VDD VLOAD AVDD AVREF AVSS Input voltage VI1 P00-P04, P10-P17 (except when used as analog input pins), P20-P27, P30-P37, X1, X2, XT2, RESET P70-P74 P110-P117, P120-P127 N-ch open drain P-ch open drain Conditions Rating -0.3 to +7.0 VDD - 40 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 -0.3 to +16Note 1 VDD - 40 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +16Note 1 Unit V V V V V V
VI2 VI3 Output voltage VO1 VO2 VO3 Analog input voltage Output current, high VAN IOH
V V V V V V mA mA mA mA mA mA mA mA mA mA mW mW C
P01-P03, P10-P17, P20-P27, P30-P37 P70-P74 P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 ANI0-ANI7 Analog input pin
VDD - 40 to VDD + 0.3 AVSS - 0.3 to AVREF + 0.3 -10 -30 -30 -120 30 15Note 2 100 60Note 2 50 20Note 2 800 600 -40 to +85
P01-P03, P10-P17, P20-P27, P30-P37 per pin P01-P03, P10-P17, P20-P27, P30-P37 total P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 per pin P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 total
Output current, low
IOL
P01-P03, P10-P17, P20-P27, P30-P37, P70-P74 per pin P70-P74 total
Peak value rms value Peak value rms value
P01-P03, P10-P17, P20-P27, P30-P37 total
Peak value rms value
Total power dissipation Operating ambient temperature Storage temperature
PTNote 3
TA = -40 to +60 C TA = +85 C
TA
Tstg
-65 to +150
C
Caution Exposure to Absolute Maximum Ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics. Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin. Notes 1. For pins to which pull-up resistors are connected by the mask option, the rating is -0.3 to VDD + 0.3. 2. To obtain the rms value, calculate [rms value] = [peak value] duty.
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Notes 3. Permissible total power loss differs depending on the temperature (see the following figure).
800
Total power loss PT [mW]
600
400
200
-40
0
+40 Temperature [C]
+80
How to calculate total power loss The following three power consumption are available for the mPD78042F. The sum of the three power consumption should be less than the total power loss PT (80 % or less of ratings is recommended).
1 2
CPU power consumption: calculate VDD (MAX.) IDD1 (MAX.). Output pin power consumption: Normal output and display output are available. Power consumption when maximum current flows into each output pin. Pull-down resistor power consumption: Power consumption by pull-down resistor connected to display output pin by the mask option.
3
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The following total power consumption calculation example assumes the case where the characters shown in the figure on the next page are displayed. Example: The operating conditions are as follows: VDD = 5 V 10 %, operating at 5.0 MHz Supply current (IDD) = 21.6 mA Display outputs: 11 grids 10 segments (cut width is 1/16) It is assumed that up to 15 mA flows to each grid pin, and that up to 3 mA flows to each segment pin. It is also assumed that all display outputs are turned off at key scan timings. Display output voltage: grid segment VO3 = VDD - 2 V (Voltage drop of 2 V is assumed.) VO3 = VDD - 0.4 V (Voltage drop of 0.4 V is assumed.)
Voltage applied to fluorescent indication panel (VLOAD) = -30 V Mask-option pull-down resistor = 25 k
The total power loss is calculated by determining power consumption conditions.
1
to
3
under the above
1 2
Power consumption of CPU: 5.5 V 21.6 mA = 118.8 mW Power consumption at output pins: total current for all grids Grid: (VDD - VO3) number of grids + 1 15 mA 11 grids 2V 11 grids + 1 (1 - 1/16) = 25.8 mW digit width (1 - cut width) =
total segment current for all dots to be lit Segment: (VDD - VO3) number of grids + 1 3 mA 31 dots 0.4 V 11 grids + 1 = 3.1 mW =
3
Power consumption at pull-down resistors: Grid: number of grids digit width = pull-down resistance number of grids + 1 (5.5 V - 2 V - (-30 V))2 11 grids (1 - 1/16) = 38.6 mW 25 k 11 grids + 1 = pull-down resistance number of grids + 1 31 dots (5.5 V - 0.4 V - (-30 V))2 = 127.3 mW 25 k 11 grids + 1 +
2
(VO3 - VLOAD) 2
Segment:
(VO3 - VLOAD) 2
number of dots to be lit
Total power consumption =
1
+
3
= 118.8 + 25.8 + 3.1 + 38.6 + 127.3 = 313.6 mW
In this example, the total power consumption does not exceed the rated value for the permissible total power loss shown in the graph on the previous page. Therefore, the calculation result in this example (313.6 mW) satisfies the requirement. If the total power consumption exceed the rated value for the permissible total power loss, the power consumption must be reduced, by reducing the number of built-in pull-down resistors.
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10-Segment/11-Digit Display Example
Display data memory
FA7AH FA79H FA78H FA77H FA76H FA75H FA74H FA73H FA72H FA71H FA70H FA6AH FA69H FA68H FA67H FA66H FA65H FA64H FA63H FA62H FA61H FA60H 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 Bit 7 Bit 6 Bit 5 Bit 4 FA7 x H Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 FA6 x H
S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 T10 T9 T8 d e f g h i j
T7
T6
T5
T4
T3
T2
T1
T0
a
b
c
i AM i PM j 0
SUN
MON
TUE j j 1 2 3
WED
THU
FRI
SAT f
a gb
4
5
6
7
8
9
edc 10 h
mPD78042F, 78043F, 78044F, 78045F
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MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = -40 to +85 C, VDD = 2.7 to 5.5 V)
Resonator Ceramic resonator Recommended circuit Parameter Oscillation frequency (fX)Note 1 Conditions MIN. 1 TYP. MAX. 5 Unit MHz
VSS X1
X2
C1
C2
Oscillation settling timeNote 2
4
ms
Crystal
VSS X1
X2
Oscillation frequency (fX)Note 1
1
4.19
5
MHz
C1
C2
Oscillation settling timeNote 2 X1 input frequency (fX)Note 1
VDD = 4.5 to 5.5 V
10 30 1 5
ms
External clock
MHz
X1
X2
PD74HCU04
X1 input high, low-level width (tXH, tXL)
100
500
ns
Notes 1. It indicates only the oscillator characteristics. For the instruction execution time, see the AC Characteristics. 2. Time required until oscillation becomes stable after VDD is applied or the STOP mode is disabled. Cautions 1. If the main system clock oscillator is to be used, wire the area inside the broken line square as follows to avoid influence of wiring capacitance: * Make wiring as short as possible. * Do not cross other signal lines. * Do not get close to lines with fluctuating large current. * Make sure that the connecting points of the capacitor of the oscillator always have the same electric potential as VSS. * Do not connect the oscillator to a ground pattern that conducts a large current. * Do not take out signal from the oscillator. 2. When switching to the main system clock again after the subsystem clock has been used with the main system clock stopped, be sure to set the program to provide enough time for the oscillation to stabilize.
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mPD78042F, 78043F, 78044F, 78045F
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = -40 to +85 C, VDD = 2.7 to 5.5 V)
Resonator Crystal Recommended circuit
XT1 XT2 VSS R C3 C4
Parameter Oscillation frequency (fXT)Note 1
Conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
Oscillation settling timeNote 2
VDD = 4.5 to 5.5 V
1.2
2 10
s
External
XT1
XT2
XT1 input frequency (fXT)Note 1
32
100
kHz
XT1 input high, lowlevel width (tXTH, tXTL)
5
15
ms
Notes 1. It indicates only the oscillator characteristics. For the instruction execution time, see the AC Characteristics. 2. Time required until oscillation becomes stable after VDD reaching MIN. of oscillation voltage range. Cautions 1. If the subsystem clock oscillator is to be used, wire the area inside the broken line square as follows to avoid influence of wiring capacitance: * Make wiring as short as possible. * Do not cross other signal lines. * Do not get close to lines with fluctuating large current. * Make sure that the connecting points of the capacitor of the oscillator always have the same electric potential as VSS. * Do not connect the oscillator to a ground pattern that conducts a large current. * Do not take out signal from the oscillator. 2. The subsystem clock oscillator is more likely to have malfunctions due to noise than the main system clock oscillator because gain for the subsystem clock oscillator is made lower to reduce current consumption. When using the subsystem clock, be careful about how to connect wires.
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mPD78042F, 78043F, 78044F, 78045F
RECOMMENDED OSCILLATOR CONSTANT MAIN SYSTEM CLOCK: CERAMIC RESONATOR (TA = -40 to +85 C)
Manufacturer Product name Frequency (MHz) Recommended circuit constant C1 (pF) Murata Mfg. Co., Ltd. CSB1000J CSA2.00MG040 CST2.00MG040 CSA4.00MG CST4.00MGW CSA5.00MG CST5.00MGW TDK Corp. CCR1000K2 CCR2.0MC3 1.00 2.00 2.00 4.00 4.00 5.00 5.00 1.00 2.00 100 100 -- 30 -- 30 -- 150 -- C2 (pF) 100 100 -- 30 -- 30 -- 150 -- Oscillator voltage range Remark
MIN. (V) 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7
MAX. (V) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Built-in capacitor Surface-mount type Built-in capacitor, surface-mount type Built-in capacitor, surface-mount type Built-in capacitor Built-in capacitor, surface-mount type Built-in capacitor Built-in capacitor Built-in capacitor, surface-mount type Built-in capacitor Built-in capacitor, surface-mount type Built-in capacitor Built-in capacitor, surface-mount type Built-in capacitor Built-in capacitor, surface-mount type Built-in capacitor Built-in capacitor Rd = 4.7 kNote
CCR4.0MC3
4.00
--
--
2.7
5.5
FCR4.0MC5 CCR5.0MC3
4.00 5.00
-- --
-- --
2.7 2.7
5.5 5.5
FCR5.0MC5 Matsushita Electronics Components Co., Ltd. EFOEC2004A4 EFOS2004B5
5.00 2.00 2.00
-- 33 33
-- 33 33
2.7 2.7 2.7
5.5 5.5 5.5
EFOEC3584A4 EFOS3584B5
3.58 3.58
33 33
33 33
2.7 2.7
5.5 5.5
EFOEC4004A4 EFOS4004B5
4.00 4.00
33 33
33 33
2.7 2.7
5.5 5.5
EFOEC5004A4 EFOS5004B5
5.00 5.00
33 33
33 33
2.7 2.7
5.5 5.5
Note When the CSB1000J (1.00 MHz) manufactured by Murata Mfg. is used, a limiting resistor (4.7 k) is necessary (see the figure in the next page). When one of other resonators is used, no limiting resistor is required. Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator that being used.
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mPD78042F, 78043F, 78044F, 78045F
Recommended sample circuit for the main system clock when the CSB1000J manufactured by Murata Mfg. is used
VSS
X1 CSB1000J
X2 Rd
C1
C2
VDD
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mPD78042F, 78043F, 78044F, 78045F
CAPACITANCE (TA = 25 C, VDD = VSS = 0 V)
Parameter Input capacitance Output capacitance Input/output capacitance Symbol CIN Conditions f = 1 MHz Unmeasured pins returned to 0 V MIN. TYP. MAX. 15 Unit pF
COUT
f = 1 MHz Unmeasured pins returned to 0 V
35
pF
CIO
f = 1 MHz Unmeasured pins returned to 0 V
P01-P03, P10-P17, P20-P27, P30-P37 P70-P74 P110-P117, P120-P127
15
pF
20 35
pF pF
Remark Unless otherwise specified, the characteristics of the shared pin are the same as the characteristics of the port pin. POWER SUPPLY VOLTAGE (TA = -40 to +85 C)
Parameter CPUNote 1 Display controller/driver PWM mode of 16-bit timer/event counter (TM0) A/D converter Other hardware Conditions MIN. 2.7Note 2 4.5 4.5 TYP. MAX. 5.5 5.5 5.5 Unit V V V
4.0 2.7
5.5 5.5
V V
Notes 1. Except for system clock oscillator, display controller/driver, and PWM. 2. Operating power supply voltage differs depending on the cycle time. See the AC Characteristics.
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mPD78042F, 78043F, 78044F, 78045F
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 2.7 to 5.5 V)
Parameter High-level input voltage Symbol VIH1 VIH2 VIH3 VIH4 VIH5 P21, P23 P00-P03, P20, P22, P24-P27, P33, P34, RESET P70-P74 X1, X2Note 2 XT1/P04, XT2Note 2 VDD = 4.5 to 5.5 V N-ch open drain Conditions MIN. 0.7VDD 0.8VDD 0.7VDD VDD - 0.5 VDD - 0.5 VDD - 0.3 VIH6 P10-P17, P30-P32, P35-P37 VDD = 4.5 to 5.5 V 0.65VDD 0.7VDD VIH7 P110-P117, P120-P127 VDD = 4.5 to 5.5 V 0.7VDD VDD - 0.5 Low-level input voltage VIL1 VIL2 VIL3 P21, P23 P00-P03, P20, P22, P24-P27, P33, P34, RESET P70-P74 VDD = 4.5 to 5.5 V 0 0 0 0 VIL4 VIL5 X1, X2Note 2 XT1/P04, XT2Note 2 VDD = 4.5 to 5.5 V 0 0 0 VIL6 VIL7 High-level output voltage VOH P10-P17, P30-P32, P35-P37 P110-P117, P120-P127 P01-P03, P10-P17, P20-P27, P30-P37, P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 P30-P37, P70-P74 VDD = 4.5 to 5.5 V IOH = -1 mA IOH = -100 mA VDD = 4.5 to 5.5 V, IOL = 15 mA VDD = 4.5 to 5.5 V, IOL = 1.6 mA VDD = 4.5 to 5.5 V, With open-drain and pull-up (R = 1 kW) IOL = 400 mA 0 VDD - 35 VDD - 1.0 TYP. MAX. VDD VDD 15Note 1 VDD VDD VDD VDD VDD VDD VDD 0.3VDD 0.2VDD 0.3VDD 0.2VDD 0.4 0.4 0.3 0.3VDD 0.3VDD Unit V V V V V V V V V V V V V V V V V V V V
VDD - 0.5 0.4 2.0
V V
Low-level output voltage
VOL1
P01-P03, P10-P17, P20-P27 VOL2
0.4
V
SB0, SB1, SCK0
0.2VDD
V
VOL3
P01-P03, P10-P17, P20-P27, P30-P37, P70-P74
0.5
V
Notes 1. Pins to which pull-up resistors are connected by the mask option become VDD. 2. If the X1 pin is used for high-level voltage input, the X2 pin is used for low-level voltage input, or vice versa. This is also true for the XT1/P04 pin and XT2 pin. Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin.
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mPD78042F, 78043F, 78044F, 78045F
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 2.7 to 5.5 V)
Parameter High-level input leakage current Symbol ILIH1 VIN = VDD Conditions P00-P03, P10-P17, P20-P27, P30-P37, RESET X1, X2, XT1/P04, XT2 VIN = 15 V P110-P117, P120-P127, VIN = VDD VIN = 0 V P70-P74 VDD = 4.5 to 5.5 V MIN. TYP. MAX. 3 Unit
mA mA mA mA mA mA mA mA mA mA
ILIH2 ILIH3 ILIH4
20 20 3Note 1 3Note 2
Low-level input leakage current
ILIL1
P00-P03, P10-P17, P20-P27, P30-P37, RESET X1, X2, XT1/P04, XT2 P70-P74 P110-P117, P120-P127
-3
ILIL2 ILIL3 ILIL4
-20 -3Note 3 -10 3
High-level output leakage current Note 4 Low-level output leakage current Note 4 Display output current Mask option pull-up resistor Software pullup resistor
ILOH1
VOUT = VDD
P01-P03, P10-P17, P20-P27, P30-P37, P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 P70-74, N-ch open drain P01-P03, P10-P17, P20-P27, P30-P37, P70-P74 P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 -15 -25
ILOH2 ILOL1
VOUT = 15 V VOUT = 0 V
20 -3
mA mA
ILOL2
VOUT = VLOAD = VDD - 35 V
-10
mA
mA k k k k k k
IOD
VDD = 4.5 to 5.5 V, VO3 = VDD - 2 V
R1
VIN = 0 V, P70-P74
20
40
90
R2
VIN = 0 V, P01-P03, P10-P17, P20-P27, P30-P37 P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 P30-P37, VIN = VDD
VDD = 4.5 to 5.5 V
15 20
40
90 500
Mask option pull-down resistor
R3
VO3 - VLOAD = 35 V VO3 - VSS = 5 V
25 15 40
65 40 80
135 90 150
R4
Notes 1. When P110 to P117 and P120 to P127 do not contain the pull-down resistors (according to the specification of the mask option), a high-level input leakage current of 150 mA (MAX.) flows only during 1.5 clocks after a read instruction has been executed to read out port 11 or 12 (P11 or P12) or port mode register 11 or 12 (PM11 or PM12). Outside the 1.5 clocks after a read instruction, the current is 3 mA (MAX.). 2. When P110 to P117 and P120 to P127 do not contain the pull-down resistors (according to the specification of the mask option), a high-level input leakage current of 90 mA (MAX.) flows only during 1.5 clocks after a read instruction has been executed to read out P11, P12, PM11, or PM12. Outside the 1.5 clocks after a read instruction, the current is 3 mA (MAX.). 3. When P70 to P74 do not contain the pull-down resistors (according to the specification of the mask option), a low-level input leakage current of -150 mA (MAX.) flows only during 1.5 clocks after a read instruction has been executed to read out port 7 (P7) or port mode register 7 (PM7). Outside the 1.5 clocks after a read out instruction, the current is -3 mA (MAX.). 4. Current which flows in the built-in pull-up or pull-down resistor is not included. Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin.
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mPD78042F, 78043F, 78044F, 78045F
DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 2.7 to 5.5 V)
Parameter Power supply current Note 1 Symbol IDD1 Conditions 5.0 MHz crystal oscillation Operating mode 5.0 MHz crystal oscillation HALT mode 32.768 kHz crystal oscillation Operating modeNote 4 32.768 kHz crystal oscillation HALT modeNote 4 XT1 = 0 V STOP mode Feedback resistor connected IDD6 XT1 = 0 V STOP mode Feedback resistor not connected VDD = 5.0 V 10 %Note 2 MIN. TYP. 7.2 0.9 1.3 550 60 35 25 5 1 0.5 0.1 0.05 MAX. 21.6 2.7 3.9 1650 120 70 50 10 20 10 20 10 Unit mA mA mA
VDD = 3.0 V 10 %Note 3 VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 %
IDD2
mA mA mA mA mA mA mA mA mA
IDD3
IDD4
IDD5
Notes 1. This current excludes the AVREF current, port current, and current which flows in the built-in pull-down resistor (mask option). 2. When operating at high-speed mode (when the processor clock control register (PCC) is set to 00H) 3. When operating at low-speed mode (when the PCC is set to 04H) 4. When the main system clock is stopped
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mPD78042F, 78043F, 78044F, 78045F
AC CHARACTERISTICS (1) Basic operation (TA = -40 to +85 C, VDD = 2.7 to 5.5 V)
Parameter Cycle time (minimum instruction execution time) TI1, 2 input frequency Symbol TCY Conditions Operated with main system clock VDD = 4.5 to 5.5 V MIN. 0.4 0.8 Operated with subsystem clock fTI VDD = 4.5 to 5.5 V 40Note 1 0 0 VDD = 4.5 to 5.5 V 250 3.6 INTP0 INTP1-INTP3 8/fsamNote 2 10 10 122 TYP. MAX. 32 32 125 2 138 Unit
ms ms ms
MHz kHz ns
tTIH TI1, 2 input high, low-level tTIL width Interrupt input high, low-level width RESET lowlevel width tINTH tINTL tRSL
ms ms ms ms
Notes 1. Value when external clock input is used as subsystem clock. When crystal is used, the value becomes 114 ms. 2. Selection of fsam = fX/2N+1, fX/64, fX/128 is available (N = 0 to 4) by bits 0 and 1 (SCS0, SCS1) of sampling clock select register (SCS).
TCY vs. VDD (with main system clock operated)
60 30 Operation guarantee range
Cycle time TCY [ s]
10
2.0 1.0 0.5 0.4
0
1
2
3
4
5
6
Power supply voltage VDD [V]
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mPD78042F, 78043F, 78044F, 78045F
(2) Serial interface (TA = -40 to +85 C, VDD = 2.7 to 5.5 V) (a) Serial interface channel 0 (i) Three-wire serial I/O mode (SCK0: Internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Conditions VDD = 4.5 to 5.5 V MIN. 800 3200 SCK0 high, low-level width tKH1 tKL1 SI0 setup time to SCK0 SI0 hold time from SCK0 SCK0OAE SO0 output delay time tSIK1 tKSI1 tKSO1 C = 100 pFNote VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKCY1/2 - 50 tKCY1/2 - 150 100 400 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns
Note C is a load capacitance of the SCK0 or SO0 output line. (ii) Three-wire serial I/O mode (SCK0: External clock input)
Parameter SCK0 cycle time Symbol tKCY2 Conditions VDD = 4.5 to 5.5 V MIN. 800 3200 SCK0 high, low-level width tKH2 tKL2 SI0 setup time to SCK0 SI0 hold time from SCK0 SCK0OAE SO0 output delay time SCK0 rise time and fall time tSIK2 tKSI2 tKSO2 C = 100 pFNote VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V 400 1600 100 400 300 1000 tR2 tF2 160 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
Note C is a load capacitance of the SO0 output line.
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mPD78042F, 78043F, 78044F, 78045F
(iii) SBI mode (SCK0: Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Conditions VDD = 4.5 to 5.5 V MIN. 800 3200 SCK0 high, low-level width tKH3 tKL3 SB0, SB1 setup time to SCK0 tSIK3 VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKCY3/2 - 50 tKCY3/2 - 150 100 300 SB0, SB1 hold time from SCK0 SCK0OAESB0, SB1 output delay time SCK0AESB0, SB1O SB0, SB1OAE SCK0O SB0, SB1 high-level width SB0, SB1 low-level width tKSI3 tKCY3/2 TYP. MAX. Unit ns ns ns ns ns ns ns
tKSO3
R = 1 kW, C = 100 pFNote
VDD = 4.5 to 5.5 V
0 0 tKCY3 tKCY3 tKCY3 tKCY3
250 1000
ns ns ns ns ns ns
tKSB tSBK tSBH tSBL
Note R is a load resistance of the SCK0, SB0, or SB1 output line, and C is its load capacitance. (iv) SBI mode (SCK0: External clock input)
Parameter SCK0 cycle time Symbol tKCY4 Conditions VDD = 4.5 to 5.5 V MIN. 800 3200 SCK0 high, low-level width tKH4 tKL4 SB0, SB1 setup time to SCK0 tSIK4 VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V 400 1600 100 300 SB0, SB1 hold time from SCK0 SCK0OAESB0, SB1 output delay time SCK0AESB0, SB1O SB0, SB1OAESCK0O SB0, SB1 high-level witdh SB0, SB1 low-level width SCK0 rise time and fall time tKSI4 tKCY4/2 TYP. MAX. Unit ns ns ns ns ns ns ns
tKSO4
R = 1 kW, C = 100 pFNote
VDD = 4.5 to 5.5 V
0 0 tKCY4 tKCY4 tKCY4 tKCY4
300 1000
ns ns ns ns ns ns
tKSB tSBK tSBH tSBL tR4 tF4
160
ns
Note R is a load resistance of the SB0 or SB1 output line, and C is its load capacitance.
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mPD78042F, 78043F, 78044F, 78045F
(v) Two-wire serial I/O mode (SCK0: Internal clock output)
Parameter Symbol tKCY5 R = 1 kW, C = 100 pFNote Conditions VDD = 4.5 to 5.5 V MIN. 1600 3800 tKCY5/2 - 160 tKCY5/2 - 50 300 600 TYP. MAX. Unit ns ns ns ns ns ns
SCK0 cycle time
SCK0 high-level width SCK0 low-level width SB0, SB1 setup time to SCK0 SB0, SB1 hold time from SCK0 SCK0OAE SB0, SB1 output delay time
tKH5 tKL5 tSIK5 tKSI5
tKSO5
VDD = 4.5 to 5.5 V
0 0
250 1000
ns ns
Note R is a load resistance of the SCK0, SB0, or SB1 output line, and C is its load capacitance. (vi) Two-wire serial I/O mode (SCK0: External clock input)
Parameter SCK0 cycle time Symbol tKCY6 Conditions VDD = 4.5 to 5.5 V MIN. 1600 3800 SCK0 high-level width SCK0 low-level width SB0, SB1 setup time to SCK0 SB0, SB1 hold time from SCK0 SCK0OAE SB0, SB1 output delay time SCK0 rise time and fall time tKH6 tKL6 tSIK6 tKSI6 650 800 100 tKCY6/2 TYP. MAX. Unit ns ns ns ns ns ns
tKSO6
R = 1 kW, C = 100 pFNote
VDD = 4.5 to 5.5 V
0 0
300 1000 160
ns ns ns
tR6 tF6
Note R is a load resistance of the SB0 or SB1 output line, and C is its load capacitance.
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mPD78042F, 78043F, 78044F, 78045F
(b) Serial interface channel 1 (i) Three-wire serial I/O mode (SCK1: Internal clock output)
Parameter SCK1 cycle time Symbol tKCY7 Conditions VDD = 4.5 to 5.5 V MIN. 800 3200 SCK1 high, low-level width tKH7 tKL7 SI1 setup time to SCK1 SI1 hold time from SCK1 SCK1OAE SO1 output delay time tSIK7 tKSI7 tKSO7 C = 100 pFNote VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKCY7/2 - 50 tKCY7/2 - 150 100 400 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns
Note C is a load capacitance of the SCK1 or SO1 output line. (ii) Three-wire serial I/O mode (SCK1: External clock input)
Parameter SCK1 cycle time Symbol tKCY8 Conditions VDD = 4.5 to 5.5 V MIN. 800 3200 SCK1 high, low-level width tKH8 tKL8 SI1 setup time to SCK1 SI1 hold time from SCK1 SCK1OAE SO1 output delay time SCK1 rise time and fall time tSIK8 tKSI8 tKSO8 C = 100 pFNote VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V 400 1600 100 400 300 1000 tR8 tF8 160 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
Note C is a load capacitance of the SO1 output line.
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mPD78042F, 78043F, 78044F, 78045F
(iii) 3-wire serial I/O mode with automatic transmission/reception function (SCK1: internal clock output)
Parameter Symbol tKCY9 Conditions VDD = 4.5 to 5.5 V MIN. 800 3200 TYP. MAX. Unit ns ns ns ns ns ns 300 1000 ns ns ns ns ns
SCK1 cycle time
SCK1 high, low-level width
tKH9 tKL9
VDD = 4.5 to 5.5 V
tKCY9/2 - 50 tKCY9/2 - 150 100 400
SI1 setup time to SCK1 SI1 hold time from SCK1 SCK1OAESO1 output delay time
tSIK9 tKSI9 tKSO9 C = 100 pFNote VDD = 4.5 to 5.5 V
SCK1AESTB* Strobe signal high level width
tSBD tSBW
tKCY9/2 - 100 tKCY9 - 30 100
tKCY9/2 + 100 tKCY9 + 30
Busy signal setup time (to busy tBYS signal detection timing) Busy signal hold time (to busy signal detection timing) Busy inactive AE SCK1O tBYH
100
ns
tSPS
2tKCY9
ns
Note C is a load capacitance of the SCK1 or SO1 output line. (iv) 3-wire serial I/O mode with automatic transmission/reception function (SCK1: external clock input)
Parameter SCK1 cycle time Symbol tKCY10 Conditions VDD = 4.5 to 5.5 V MIN. 800 3200 SCK1 high, low-level width tKH10 tKL10 SI1 setup time to SCK1 SI1 hold time from SCK1 SCK1OAE SO1 output delay time SCK1 rise time and fall time tSIK10 tKSI10 tKSO10 C = 100 pFNote VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V 400 1600 100 400 300 1000 tR10 tF10 160 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
Note C is a load capacitance of the SO1 output line.
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mPD78042F, 78043F, 78044F, 78045F
AC timing test points (except X1, XT1 input)
0.8VDD 0.2VDD
Test points
0.8VDD 0.2VDD
Clock timing
1/fX tXL tXH VDD - 0.5 V X1 input 0.4 V
1/fXT tXTL tXTH VDD - 0.5 V XT1 input 0.4 V
TI timing
1/fTI tTIL tTIH
TI1, TI2
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mPD78042F, 78043F, 78044F, 78045F
Serial transfer timing 3-wire serial I/O mode:
tKCY1, 2, 7, 8 tKL1, 2, 7, 8 tR2, 8 SCK0, SCK1 tKH1, 2, 7, 8 tF2, 8
tSIK1, 2, 7, 8
tKSI1, 2, 7, 8
SI0, SI1
Input data
tKSO1, 2, 7, 8
SO0, SO1
Output data
SBI mode (bus release signal transfer):
tKCY3, 4 tKL3, 4 tR4 SCK0 tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 tF4
SB0, SB1 tKSO3, 4
SBI mode (command signal transfer):
tKCY3, 4 tKL3, 4 SCK0 tSIK3, 4 tKH3, 4
tKSB
tSBK
tKSI3, 4
SB0, SB1 tKSO3, 4
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mPD78042F, 78043F, 78044F, 78045F
2-wire serial I/O mode:
tKCY5, 6 tKL5, 6 tR6 SCK0 tKSO5, 6 tSIK5, 6 tKH5, 6 tF6
tKSI5, 6
SB0, SB1
3-wire serial I/O mode with automatic transmission/reception function:
SO1
D2
D1
D0
D7
SI1
D2 tSIK9, 10 tKSO9, 10
D1 tKSI9, 10 tKH9, 10
D0
D7
tF10 SCK1 tKL9, 10 tKCY9, 10 STB tR10 tSBD tSBW
3-wire serial I/O mode with automatic transmission/reception function (busy processing):
SCK1
7
8
9Note
10Note tBYS
10 + nNote tBYH tSPS
1
BUSY (Active high)
Note SCK does not become low actually at this point, but is indicated so to conform to the timing specification.
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mPD78042F, 78043F, 78044F, 78045F
A/D CONVERTER CHARACTERISTICS (TA = -40 to +85 C, AVDD = VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Total errorNote 1 Conversion timeNote 2 tCONV tSAMP VIAN 1 MHz - fX - 5.0 MHz 19.1 2.86 AVSS Symbol Conditions MIN. 8 TYP. 8 MAX. 8 0.8 200 30 AVREF Unit bit %
ms ms
V
Sampling timeNote 3 Analog signal input voltage Reference voltage AVREF resistor AVDD current
AVREF RAVREF AIDD
4.0 4 14 200
AVDD
V k
400
mA
Notes 1. Quantization error (1/2LSB) is not included. This parameter is indicated as the ratio to the full-scale value. 2. Set the A/D conversion time to 19.1 ms or more. 3. Sampling time depends on the conversion time.
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mPD78042F, 78043F, 78044F, 78045F
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = -40 to +85 C)
Parameter Data retention supply voltage Data retention supply current Symbol VDDDR Conditions MIN. 2.0 TYP. MAX. 5.5 Unit V
IDDDR
VDDDR = 2.0 V Subsystem clock stopped Feedback resistor not connected 0 Release by RESET Release by interrupt
0.1
10
mA
Release signal set time Oscillation stabilization wait time
tSREL tWAIT
ms
217/fX
Note
ms ms
Note Selection of 212/fX, 214/fX to 217/fX is available by bits 0 to 2 (OSTS0 to OSTS2) of oscillation settling time select register (OSTS). Data retention timing (STOP mode release by RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operating mode
VDD STOP instruction execution
VDDDR
tSREL
RESET
tWAIT
Data retention timing (standby release signal: STOP mode release by interrupt signal)
HALT mode STOP mode Data retention mode Operating mode
VDD STOP instruction execution
VDDDR
tSREL
Standby release signal (interrupt request) tWAIT
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Interrupt input timing
tINTL tINTH
INTP0-INTP2
tINTL
INTP3
RESET input timing
tRSL
RESET
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11. CHARACTERISTIC CURVE (REFERENCE VALUE)
IDD vs. VDD (Main system clock: 5.0 MHz) (TA = 25 C) 10.0
PCC = 00H
5.0
PCC = 01H PCC = 02H PCC = 03H PCC = 04H PCC = 30H HALT (X1 and XT1 oscillate)
1.0
0.5
Supply current IDD [mA]
fX = 5.0 MHz fXT = 32.768 kHz
0.1
PCC = B0H
0.05
HALT (X1 stops but XT1 oscillates) STOP (X1 stops but XT1 oscillates)
0.01
0.005
0.001 0 2 3 4 5 6 7 8 Supply voltage VDD [V]
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IDD vs. fX (VDD = 3 V, TA = 25 C) 4
PCC = 00H
3
Supply current IDD [mA]
2
PCC = 01H
1
PCC = 02H PCC = 03H PCC = 04H HALT (X1 oscillates)
0
0
1
2
3
4
5
6
Clock oscillation frequency fX [MHz]
IDD vs. fX (VDD = 5 V, TA = 25 C) 7 6 5
PCC = 00H
Supply current IDD [mA]
4
PCC = 01H
3 2
PCC = 02H PCC = 03H PCC = 04H HALT (X1 oscillates)
1 0 0 1 2 3 4
5
6
Clock oscillation frequency fX [MHz]
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VOL vs. IOL (Port 1) (TA = 25 C)
30
VDD = 6 V
VDD = 5 V VDD = 4 V
Low-level output currnt IOL [mA]
VDD = 3 V 20
10
0 0 0.5 1.0 1.5
Low-level output voltage VOL [V]
VOL vs. IOL (Ports 0, 2, and 3) (TA = 25 C)
30
VDD = 6 V VDD = 5 V
VDD = 4 V
Low-level output current IOL [mA]
VDD = 3 V 20
10
0 0 0.5 1.0 1.5
Low-level output voltage VOL [V]
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VOL vs. IOL (Port 7) (TA = 25 C)
30
VDD = 6 V
VDD = 5 V
VDD = 4 V
Low-level output current IOL [mA]
VDD = 3 V 20
10
0 0 0.5 1.0 1.5
Low-level output voltage VOL [V]
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VDD - VOH vs. IOH (Port 0 - Port 3) (TA = 25 C) VDD = 5 V VDD = 6 V VDD = 4 V VDD = 3 V
High-level output current IOH [mA]
-10
-5
0 0 0.5 1.0 1.5
High-level output voltage VDD - VOH [V]
VDD - VOH vs. IOH (Port 8 - Port 12) (TA = 25 C)
-30
VDD = 6 V VDD = 5 V
High-level output current IOH [mA]
VDD = 4 V VDD = 3 V -20
-10
0 0 1.0 2.0 3.0
High-level output voltage VDD - VOH [V]
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12. PACKAGE DRAWING 5
80 PIN PLASTIC QFP (14 20)
A B
64 65
41 40
detail of lead end
CD
S Q R
80 1
25 24
F G H P I
M
J
K M N L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 1.0 0.8 0.350.10 0.15 0.8 (T.P.) 1.80.2 0.80.2 0.15 +0.10 -0.05 0.10 2.7 0.10.1 55 3.0 MAX. INCHES 0.9290.016 0.795 +0.009 -0.008 0.551 +0.009 -0.008 0.6930.016 0.039 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.0040.004 55 0.119 MAX. P80GF-80-3B9-3
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
Remark The shape and material of the ES version are the same as those of the corresponding mass-produced product.
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13. RECOMMENDED SOLDERING CONDITIONS
The conditions listed below shall be met when soldering the mPD78042F, mPD78043F, mPD78044F, or
mPD78045F.
For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting
Technology Manual (C10535E).
Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 13-1 Soldering Conditions for Surface-Mount Devices
-3B9: 80-pin plastic QFP (14 20 mm) mPD78042FGF- -3B9: 80-pin plastic QFP (14 20 mm) mPD78043FGF- -3B9: 80-pin plastic QFP (14 20 mm) mPD78044FGF- -3B9: 80-pin plastic QFP (14 20 mm) mPD78045FGF-
Soldering process Infrared ray reflow Soldering conditions Peak package's surface temperature: 235 C Reflow time: 30 seconds or less (210 C or more) Maximum allowable number of reflow processes: 3 Peak package's surface temperature: 215 C Reflow time: 40 seconds or less (200 C or more) Maximum allowable number of reflow processes: 3 Solder temperature: 260 C or less Flow time: 10 seconds or less Number of flow processes: 1 Preheating temperature : 120 C max. (measured on the package surface) Terminal temperature: 300 C or less Heat time: 3 seconds or less (for one side of a device) Recommended conditions IR35-00-3
VPS
VP15-00-3
Wave soldering
WS60-00-1
Partial heating method
--
Caution Do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections).
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APPENDIX A DEVELOPMENT TOOLS
The following tools are available for development of systems using the mPD78042F, mPD78043F, mPD78044F, or mPD78045F. Language processing software
RA78K/0Notes 1, 2, 3, 4 CC78K/0Notes 1, 2, 3, 4 DF78044Notes 1, 2, 3, 4 CC78K/0-LNotes 1, 2, 3, 4 Assembler package common to 78K/0 series C compiler package common to 78K/0 series Device file for mPD78044A subseries C compiler library source file common to 78K/0 series
PROM writing tools
PG-1500 PA-78P048GF PA-78P048KL-S PG-1500 controllerNotes 1, 2 PROM programmer Programmer adapter connected to PG-1500
Control program for PG-1500
Debugging tools
IE-78000-R IE-78000-R-ANote 8 IE-78000-R-BK IE-78044-R-EM EP-78130GF-R EV-9200G-80 SM78K0Notes 5, 6, 7 ID78K0Notes 4, 5, 6, 7, 8 SD78K/0Notes 1, 2 DF78044Notes 1, 2, 5, 6, 7 In-circuit emulator common to 78K/0 series In-circuit emulator common to 78K/0 series (for integrated debugger) Break board common to 78K/0 series Emulation board for evaluating mPD78044A subseries Emulation probe common to mPD78134 Socket mounted on target system created for 80-pin plastic QFP System simulator common to 78K/0 series Integrated debugger for IE-78000-R-A Screen debugger for IE-78000-R Device file common to mPD78044A subseries
5
5
Real-time OS
RX78K/0Notes 1, 2, 3, 4 MX78K0Notes 1, 2, 3, 4 Real-time OS for 78K/0 series OS for 78K/0 series
Notes 1. PC-9800 series (MS-DOSTM) based 2. IBM PC/ATTM and compatible (PC DOSTM/IBM DOSTM/MS-DOS) based 3. HP9000 series 300TM (HP-UXTM) based 4. HP9000 series 700TM (HP-UX) based, SPARCstationTM (SunOSTM) based, EWS-4800 series (EWSUX/V) based 5. PC-9800 series (MS-DOS + Windows TM) based 6. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based 7. NEWSTM (NEWS-OSTM) based 8. Under development 5
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Fuzzy inference development support system
FE9000Note 1/FE9200Note 3 FT9080Note 1/FT9085 Note 2 FI78K0Notes 1, 2 FD78K0Notes 1, 2 Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
Notes 1. PC-9800 series (MS-DOS) based 2. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS) based 3. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party development tools. 2. RA78K/0, CC78K/0, SM78K/0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78044.
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APPENDIX B RELATED DOCUMENTS
* Documents Related to Devices
Document No. Document name Japanese English U10908E This manual U10611E -- IEU-1372 -- --
mPD78044F Sub-Series User's Manual mPD78042F, 78043F, 78044F, 78045F Data Sheet mPD78P048A Data Sheet mPD78044A, 78044F Sub-Series Special Function Registers
78K/0 Series User's Manual, Instruction 78K/0 Series Instruction Summary Sheet 78K/0 Series Instruction Set
U10908J U10700J U10611J U10701J IEU-849 U10903J U10904J
* Documents Related to Development Tools (User's Manual)
Document No. Document name Japanese RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler Operation Language CC78K/0 Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) Base PG-1500 Controller IBM PC Series (PC DOS) Base IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78044-R-EM EP-78130GF-R SM78K0 System Simulator SM78K Series System Simulator Reference External Parts User Open Interface Specifications Reference Tutorial Reference Tutorial Reference Programming Know-How EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEA-618 EEU-777 EEU-651 EEU-704 EEU-5008 EEU-810 U10057J EEU-867 EEU-833 EEU-943 EEU-5002 U10092J English EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 EEA-1208 -- EEU-1335 EEU-1291 U10540E U11376E U10057E EEU-1427 EEU-1424 EEU-1470 U10181E U10092E
5
ID78K0 Integrated Debugger SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Base SD78K/0 Screen Debugger IBM PC/AT (PC DOS) Base
U11151J EEU-852 EEU-816 EEU-5024 U11279J
-- U10539E -- EEU-1414 EEU-1413
5
Caution The above documents may be revised without notice. Use the latest versions when you design an application system.
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* Documents Related to Software to Be Incorporated into the Product (User's Manual)
Document No. Document name Japanese 78K/0 Series Real-Time OS Basic Installation Technical OS for 78K/0 Series MX78K0 Tool for Creating Fuzzy Knowledge Data 78K/0, 78K/II, and 87AD Series Fuzzy Inference Development Support System, Translator 78K/0 Series Fuzzy Inference Development Support System, Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System, Fuzzy Inference Debugger EEU-858 EEU-1441 Basic EEU-912 EEU-911 EEU-913 EEU-5010 EEU-829 EEU-829 English -- -- -- -- EEU-1438 EEU-1444
EEU-921
EEU-1458
* Other Documents
Document No. Document name Japanese English
5
IC PACKAGE MANUAL SMD Surface Mount Technology Manual Quality Grades on NEC Semiconductor Device NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Device Guide for Products Related to Micro-Computer: Other Companies
C10943X C10535J IEI-620 C10983J MEM-539 MEI-603 MEI-604 C10535E IEI-1209 C10983E -- MEI-1202 --
Caution The above documents may be revised without notice. Use the latest versions when you design an application system.
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[MEMO]
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Cautions on CMOS Devices
Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. Also handle boards on which MOS devices are mounted in the same way. CMOS-specific handling of unused input pins Caution Hold CMOS devices at a fixed input level. Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediatelevel input may be caused by noise. This allows current to flow in the CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the VDD or GND pin through a resistor. If handling of unused pins is documented, follow the instructions in the document. Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on. Since characteristics of a MOS device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. NEC has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. However, NEC assures operation after reset and items for mode setting if they are defined. When you turn on a device having a reset function, be sure to reset the device first.
FIP is a trademark of NEC Corporation. IEBus is trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of SONY Corporation.
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Mountain View, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby Sweden Tel: 8-63 80 820 Fax: 8-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 3
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Note that "preliminary" is not indicated in this document, even though the related documents may be preliminary versions.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product.
M4 94. 11
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